This relates generally to integrated circuits, and more particularly, to circuitry such as memory circuitry that may incorporate stressed transistors.
There is a trend with each successive generation of integrated circuit technology to scale transistors to smaller sizes, smaller threshold voltages, and smaller power supply voltages. Made properly, these adjustments allow improved performance and lowered costs. Care must be taken, however, to avoid issues such as excessive power consumption.
One aspect of lowering power consumption on an integrated circuit relates to transistor leakage currents. Leakage currents are undesired currents that flow between the terminals of a transistor during operation. An ideal transistor would exhibit no leakage. In the real world, however, leakage currents are unavoidable and must be minimized as best possible. If leakage currents are too high, a circuit may exhibit unacceptably large static power consumption. Particularly in circuits with large numbers of transistors, such as modern integrated circuits that include memory cells, leakage current minimization can be highly beneficial.
A technique that has often been used to reduce transistor leakage currents involves forming transistors with increased threshold voltages. Transistors generally have four terminals. The four transistor terminals include a drain terminal, a gate terminal, a source terminal, and a bulk terminal. The total leakage current of a transistor includes current contributions from a source-drain leakage current and a bulk leakage current. The source-drain leakage current is an undesired leakage current that flows between the drain and source terminals. The bulk leakage current is an undesired leakage current that flows between the drain and bulk terminals (or between the source and bulk terminals).
At previous technology nodes (e.g., in circuits having transistors with gate lengths greater than 45 nm), increasing the threshold voltage of a transistor would reduce its total leakage current. This is because increases in the threshold voltage of a transistor tended to lower the source-drain leakage current significantly while causing only minimal increases in bulk leakage current. Because the decrease in source-drain leakage current is greater than the increase in bulk leakage current, total leakage current is reduced.
Increases to the threshold voltages of these transistors are typically achieved by increasing channel doping. For example, a pocket implant may be performed during fabrication of a transistor. The pocket implant introduces a high concentration of dopant into regions of the channel that are adjacent to the source and drain terminals and increases threshold voltage.
As transistors continue to scale to gate lengths below 45 nm, however, increasing threshold voltages in this way increases bulk leakage significantly. This increase in bulk leakage can be greater than the decrease in source-drain leakage. As a result, increasing transistor threshold voltages may lead undesired increases in total leakage currents.
It would therefore be desirable to be able to provide improved techniques for forming transistors with reduced leakage.